International Journal of Computer
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Volume 3 | Issue 3 | Year 2012 | Article Id. IJCTT-V3I3P126 | DOI : https://doi.org/10.14445/22312803/IJCTT-V3I3P126

Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI

M.Padmaja, V.N.V. Satya Prakash

Citation :

M.Padmaja, V.N.V. Satya Prakash, "Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI," International Journal of Computer Trends and Technology (IJCTT), vol. 3, no. 3, pp. 467-471, 2012. Crossref, https://doi.org/10.14445/22312803/IJCTT-V3I3P126

Abstract

The Low power and low energy has become an important issue in today’s consumer electronics. Any combinational circuit can be represented as a multiple inputs with single output. Multiplexers are used to design any digital combinational logic circuit. Hence it is required to design a multiplexer with low power consumption and high speed. The main objective of this paper is to design the multiplexer using complementary metal oxide semiconductor (CMOS) logic and

Keywords

CMOS, Low power, High Speed, Area.

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